PCI9054-based nterface card design

PCI bus supports burst transfer, multi-processor and concurrent work, are widely used in a variety of platform design. PCI9054-based interface board is also widely used in various high-speed, large amount of data processing systems. As a PCI bus and bridge PCI9054 local bus, developers do not have too much to consider complex PCI bus specification, and thus have more energy developed hardware and driver design.
here to PCI9054, for example, gives the interface board hardware and software design, detail design of the system schematic and VHDL language source code written in some logic, for the relevant developer reference.
1PCI9054 About
PCI9054 PLX launch is a 32-bit 33MHz PCI bus master I / O accelerators, it uses PLX industry-leading data pipelining framework includes DMA engine, programmable PCI initiator and target data transfer mode, and PCI messaging functions. PCI2.2 version of the specification to follow, get up to 132MB / s burst transfer rate. It makes the application of complex PCI interface design becomes relatively simple, has become one of the mainstream PCI interface device.
PCI9054 data in 3 ways: the main mode, slave mode and DMA mode. Its internal data with two DMA channels, each channel supports block Scatter / Gather DMA way, two-way data path of 6 FIF0 data buffer, can simultaneously receive and transmit high-speed data, eight 32-bit Mailbox register for two-way data path to provide messaging, PCI9054 internal block diagram, shown in Figure 1.
PCI9054 local bus with M, C, J3 modes, can be mode selection pin MODE [1:0] control, where C model to meet most application requirements, and the C mode of operation of local bus timing of the most simple, logical control is relatively easy, the difficulty of its development is relatively low. C mode, the PCI9054 chip logic control through the PCI address and data lines separate, easily providing the timing for the local working practices, are generally more widely used in system design. Therefore, if no special needs, recommended C mode, which is the interface card used in the model, while PCI9054 local bus clock can be externally provided, the clock and PCI clock can be asynchronous.
2 interface card hardware design
interface card main functions are: a working model of the peripheral devices and state detection, control side of the test results for the corresponding data receive or transmit operation . The workflow is: a request by the control side, according to the signals into the interface card for external devices to detect and work patterns and the state to decide whether to enter the peripheral signals received or transmitted. Mechanical properties, the interface cards comply with the Eurocard industry standard, the use of 6U (233.35mmxl60mm) structure. Interface card logic diagram shown in Figure 2.
see from Figure 2, interface cards are divided into three parts: PCI bus interface The local bus interface and serial EEPROM interface.
2.1PCI9054 and PCI bus interface
PCI9054 and PCI bus interface is actually connected with the cPCI connector Jl PCI9054 connection that PCI9054 PCI-ended signal line through 10Ω termination resistor and the corresponding PCI slot corresponds to the signal line connection. PCI bus interface signals include address data multiplex signal line, the interface control signal lines, interrupt lines. PCB design, in order to satisfy the reflection conditions, the need to pay attention to the PCI bus signal routing and length, the length of regular signal from the connector to the PCI bridge device spacing should not exceed 1.5 inches (3.81cm), PCI_CLK signal wiring length 2.5 ± 0.1 inches, otherwise it will lead to signal instability or even a bus conflict will not boot. PCI9054 internal programmable FIF0, zero-wait burst and the local bus and PCI bus asynchronous operation, provided by an external local bus clock, The clock and PCI clock (33MHz) asynchronous, choose to work in the 50MHz local bus by the frequency of 50MHz crystal OSCl produced at the same time sent to the PCI9054 Local clock signal LCLK and sent to the CPLD clock signal CCLK to wait long to keep them synchronized.
2.2PCI9054 with the local bus interface
in the interface card using Xilinx CPLD produced XC95288XL, to achieve the interface card logic control. C mode, the PCI9054 chip logic control through the PCI address and data lines separately, and then correspond with the CPLD pin connections, can facilitate the timing of work to provide a variety of local work, generally used in system design.
local bus section INPUT_BUFFER some of the major component by the differential voltage comparator shown in Figure 3. When the incoming signal voltage from J4 (pin 7) is greater than the reference voltage (pin 6), the output high (pin 1) and into the CPLD, PCI9054 controller reads. 0UT_BUFFER component is the controller for the peripheral to receive or send data control.
2.3PCI9054 and EEPROM interface
PCI9054 provides 4-pin EEDI, EED0, EESK, EECS and serial EEPROM-93LC5 * pin DI, D0, SK, CS connected, in addition to the VCC pin to pick up 93LC56 3.3 V power supply, GND to ground. Because of the need to write to the serial EEPROM, serial EEPROM is programmable and non-need state protection, so the PE through the 10kΩ resistor pullup followed by high voltage of 3.3V, while the PRE through the 10kΩ resistor pulldown to ground . EEPROM schematic shown in Figure 4.
connected PCI9054 and PCI bus interface, local bus interface and serial EEPROM interface , the need for register configuration, the configuration tool is required by means of Windriver, register configuration includes the configuration of the PCI configuration registers, the configuration and local configuration registers initialized to the EEPROM.
configure the PCI configuration register is fill out the manufacturer of the main ID number, device ID, subsystem vendor ID number and production sub-category code ID number. For the PCI9054, the raw vendor ID number, device ID, subsystem number, ID number and other subsystem is fixed, can be found in the PCI9054 data manual.
local configuration register is configured on the local properties of the local bus address space and configuration, this configuration based on the actual development needs, the configuration is complete, the host CPU to access the local address space, may give the corresponding PCI bus address.
PCI9054 at power-up, the initialization data read from an external EEPROM to configure the PCI9054 internal registers in the board during POST Calgary, PCI bus RST # signal resets, PCI9054 internal register default response. PCI9054 local LRESET # signal and the detection of serial EEPROM.
If the serial EEPROM 33 in the first failure is 1, then the PCI9054 serial EEPROM to determine the non-empty, users can register to the PCI9054 CNTRL 29-bit write 1 to load the contents of the EEPROM to the PCI9054 internal registers, configuration information can be P1xSdk of PLXMON under the EEPROM configuration.
3 interface card software design
3.1CPLD logic design
PC39054 by local bus and local bus devices to communicate, PCI9054 provides two kinds of access methods, namely, single-cycle and burst access.
which uses single-cycle access to local bus for local bus interface state machine control, the state diagram shown in Figure 5. SO for the idle state, when the ADS # 0, such as by local bus decode logic decoding the space that is needed to access the local state S1, or remain in the state of SO; state S1 is a single-cycle access to the start state, When BLAST # is 1, stay in state S1, or else go to state S2: state S2 to access wait state, this state data is maintained in the local bus, and then go directly to the state S3; state S3 data transfer state, in this state data is removed from the local bus (if necessary you can add a state to extend reading time data); When ADS # is 0, the local bus decode logic decoding, the show also needs access to the local space, go to state S1, or converted to SO, the end of the cycle, access to complete data transfer.
the above state machine in VHDL language to implement a programmable device, part of the source code is as follows:


With XilinxISE9.1i Figure 6 is a simulation tool in C mode 8-bit local bus width of the local logic control of transmission timing simulation results for example. See from Figure 6: In the write cycle, the address of the PCI bus side local_adrr [9:2] to write output data 8 00 outport0; the read cycle, is to address 8 00 data from inportO [2; 0] read into local_data [0].
3.2 driver design
Windriver is Jungo production of a device driver development kit, developers need to familiar with the operating system kernel device driver development using Windriver. The driver in user mode all functions are running, with Windriver . Vxd or. Sys file drive hardware interaction to achieve the purpose of greatly improving the PCI device driver development.
Windriver driver development using the process as follows: First, open Windriver equipment, look for the PCI device to be accessed; then enumerate the device resources (including memory, I / O, interrupt) and lock the device resources, other programs can not be accessed; to access the resources of the board is unlocked after the resource; finally closed Windriver equipment. This process is written in C language development environment in VC 6.0 Windriver itself comes under the help function (Windriver after installation, in its “Help” function can identify the relevant instructions) to achieve the PCI9054
< br /> initialized. Device open access to hardware resources, call the library, the device closure operation. Then the source code to compile, link and run successfully, to find out the five documents: wdr-eg. exe, plx9054. inf, windrvr6. sys, plx9054. lib and plx9054. dll, the five files make up the required driver files. Successfully inserted into the card slot and click wdreg. exe successfully install the driver.
4 Conclusion
In this paper, the higher cost of PCI9054 PCI bridge device as given some of the features described bridge device, circuit design should pay attention to the problems and local bus data transfer interface logic design. This design reduces the complexity of the PCI bus, the PCI bus for easy side of the controller on the local bus and local bus mode and external equipment status effective detection, has great application value.